I create a new CORE Generator project with a specific part and everything with the GUI is fine. Then, I change the design entry type from VHDL to Verilog.
Now, if I save and close the project without exiting CORE Generator and then I reopen the project, all of the IP are grayed out (disabled). If I click on the button Only IP compatible with chosen part, no IPs are shown.
Why does this occur?
The problem is that the IPCompatibilityChecker is not refreshed correctly when the project is reopened. Because the correct part is not loaded, no IP will be found to match the part.
The issue is fixed in ISE Design Suite 14.3.