UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55843

14.2 CORE Generator - No IP appears after reopening CORE Generator project and selecting "Only IP compatible with chosen part"

描述

I create a new CORE Generator project with a specific part and everything with the GUI is fine. Then, I change the design entry type from VHDL to Verilog.
Now, if I save and close the project without exiting CORE Generator and then I reopen the project, all of the IP are grayed out (disabled).  If I click on the button Only IP compatible with chosen part, no IPs are shown.

Why does this occur?

解决方案

The problem is that the IPCompatibilityChecker is not refreshed correctly when the project is reopened.  Because the correct part is not loaded, no IP will be found to match the part.

The issue is fixed in ISE Design Suite 14.3.

AR# 55843
日期 07/01/2013
状态 Archive
Type 综合文章
器件
  • Virtex-6
Tools
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
的页面