Version Found: v1.9
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)
In some MIG 7 Series RLDRAM3 designs, data failures (or lack of data) can occur after reset and calibration has completed.
The failure rate seen can vary but has been seen to be as low as 1 out of 20,000 resets.
A new update to the RLDRAM3 initialization which holds the PHASER_IN in reset until the QK/QK# clocks are stable will prevent these data failures from occurring.
This issue has only been seen with RLDRAM3 devices but the update is also included for QDRII+ and RLDRAM II designs.
The ZIP file at the end of this answer record contains the updated RTL with instructions on how to apply the updates.
05/07/2013 - Initial release