Version Found: v1.9a
Version Resolved: See (Xilinx Answer 54025)
MIG 7 Series RLDRAM3 v1.9a design does not allow data to be placed on T0 or T3 byte groups when DM and Internal Vref are enabled even though this is a valid configuration.
This only occurs in the MIG GUI during IP generation when using the Bank Selection mode.
To work around the issue and to place data pins on T0 or T3 byte groups when DM and Internal Vref are enabled, the "Fixed Pin Out" mode can be used.
06/19/2013 - Initial release