UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56229

MIG 7 Series RLDRAM II / 3 - Timing failures can be seen in the MIG generated example for multi-controller designs when the Debug Port is enabled

描述

Version Found: v1.9.a
Version Resolved: See (Xilinx Answer 54025)

For MIG 7 series RLDRAM multi-controller designs, it is possible for the following paths to fail timing in the MIG generated Example Design when the Debug Port is enabled:

From:

u_my_mig/c1_u_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_phy_read_top/
u_qdr_rld_phy_read_stage2_cal/cal_done_reg/C

To:

CHIPSCOPE_INST.u_ila_rldx/inst/ila_core_inst/shifted_data_in_reg[6][527]_srl7/D

From

c1_u_traffic_gen_top/u_memc_traffic_gen/tg_status/error_set_reg/C

To:

CHIPSCOPE_INST.u_ila_rldx/inst/ila_core_inst/shifted_data_in_reg[6][1]_srl7/D

解决方案

If you see these timing failures, the following code changes can be made in example_top.v/ to resolve them:

Change:

    (*mark_debug = "TRUE" *) wire         c0_dbg_tg_compare_error;  

   (*mark_debug = "TRUE" *) wire          c0_dbg_init_calib_complete;

  assign init_calib_complete = c0_init_calib_complete & c1_init_calib_complete;

  assign tg_compare_error = c0_tg_compare_error | c1_tg_compare_error;

  assign c0_dbg_tg_compare_error = tg_compare_error;

 assign c0_dbg_init_calib_complete = init_calib_complete;

    .PROBE1 (c0_dbg_tg_compare_error),  

    .PROBE97(c0_dbg_init_calib_complete )

To (please see the changes in bold):

  //  (*mark_debug  = "TRUE" *) wire          c0_dbg_tg_compare_error;  

  //  (*mark_debug  = "TRUE" *) wire          c0_dbg_init_calib_complete;

  assign init_calib_complete = c0_init_calib_complete & c1_init_calib_complete;

  assign tg_compare_error = c0_tg_compare_error | c1_tg_compare_error;

  // assign c0_dbg_tg_compare_error = tg_compare_error;

  // assign c0_dbg_init_calib_complete = init_calib_complete;

    .PROBE1 (c0_tg_compare_error ),  

    .PROBE97(c0_init_calib_complete )

Revision History
07/18/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 56229
日期 07/21/2015
状态 Active
Type 已知问题
器件
IP
的页面