AR# 5633


FPGA Express: Syntax error at or near token 'bxx (VE-0)


Keywords: Express, VE-0, token, define, verilog

Urgency: Standard

General Description: Express produces an error when the user
either synthesizes or checks syntax:

Error: syntax error at or near token 'bxx (VE-0)

where xx is some number. The line in question is using a `define
in Verilog to set the width of a wire or reg as shown:

data = `DATA_BUS_WIDTH'b0;

where there exists:

`define DATA_BUS_WIDTH 14


This particular syntax is not supported by Synopsys compilers.
The user must replace the width specification by a number.
For example:

data = 14'b0;
AR# 5633
日期 08/27/2001
状态 Archive
Type 综合文章
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