This states that we want an external 100 MHz system clock.
If we look at the chipscope_ibert_top.ucf, (in chipscope_ibert/example_design folder) I see this:
# Sysclk Timing Constraints
# External Clock Source
NET "IBERT_SYSCLOCK_P_IPAD" PERIOD = 156.25 MHz;
This tells us that the sysclk frequency encoded in the core is wrong, and it is 156.25.
This equation below can be used to correlate the line rate seen in the IBERT Analyzer GUI to the actual line rate running on the hardware.
Actual line rate = reported line rate in GUI * (correct sysclk freq / UCF sysclk frequency)
Actual line rate = 4.688 * (100 / 156.25 ) = 3.000
4.688 is the line rate being displayed in the IBERT Analyzer GUI
100 is the system clock frequency I entered into the ChipScope CORE Generator GUI
156.25 is the system clock frequency that is in the UCF file (actual system clock frequency expected)
3.000 is the line rate I expected to be running in the hardware, and is the expected value that should be displayed in the IBERT analyzer GUI.
Also note that if I had supplied the core with a 156.25 (expected sysclk frequency), I would see 3.000 as the correct line rate in the IBERT analyzer GUI.