AR# 56376

LogiCORE DUC/DDC Compiler v3.0 - Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation

描述

Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation. The output of the core, SREG_PRDATA, will be all-X.

解决方案

This is a known issue with DUC/DDC Compiler v3.0.

A workaround is to use Mentor Graphics ModelSim or QuestaSim as the simulator for behavioral simulation. This may be configured in the Vivado GUI project options dialog.

For a detailed list of LogiCORE IP DUC/DDC Compiler Release Notes and Known Issues, see (Xilinx Answer 54476).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54476 LogiCORE IP DUC/DDC Compiler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56376
日期 07/01/2013
状态 Active
Type 综合文章
Tools
IP