AR# 56385


MIG 7 Series DDR3 - timing failures can occur with larger SSI devices


Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

Timing failures can be seen when targeting the larger SSI devices (i.e. 2000T) as a result of the XADC being located in a different SLR then the rest of the MIG design.


This failure has only been seen with multi-controller designs where the XADC is located two or more SLR's away from the SLR region in which the memory interface is located. The multi-cycle constraints need to be updated to accurately reflect the worst case scenario of rstdiv0_sync crossing multiple SLRs to reach the XADC and 1 Buffer. The following constraints need to be replaced in the XDC constraint file if timing failures are seen. 

set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] \                     -setup 2 -end set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] \                     -hold 1 -end


set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] \                     -setup 5 -end  set_multicycle_path -to   [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] \                     -hold 4 end

Revision History
06/19/2013 - Initial release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 56385
日期 10/13/2013
状态 Active
Type 已知问题
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