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AR# 56587

2013.2 Vivado IP Integrator - READ/WRITE_OUTSTANDING parameter is not getting populated to the AXI_7Series MIG S_AXI port in Vivado IPI


I have a simple IPI design consisting of a 7 series MIG, AXI Interconnect and a Reset IP. 

I have the AXIslave port connected externally.

I have the read/write outstanding set to 4.

However, if I generate the output product and monitor the 7 series s_axi port properties, the read/write outstanding is set to 8 and is grayed out and cannot be changed.

How can I set this manually?


To work around this (using the example above),  use the Tcl command below:

set_param bd.propagate.allow_set_readonly_param 1
set_property CONFIG.NUM_READ_OUTSTANDING 4 [get_bd_intf_pins /mig_7series_1/S_AXI]
set_property CONFIG.NUM_WRITE_OUTSTANDING 4 [get_bd_intf_pins /mig_7series_1/S_AXI]

Note: The command set_param bd.propagate.allow_set_readonly_param 1 should to be used carefully.

This issue has been fixed starting in Vivado 2013.3.

AR# 56587
日期 11/21/2014
状态 Archive
Type 综合文章
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2012.3
  • MIG 7 Series