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AR# 56612

Vivado IP Integrator Solution Center


The Xilinx Vivado IP Integrator Solution Center is available to address all questions related to the Xilinx Vivado IP Integrator tool. Whether you are starting a new IP Integrator design, or troubleshooting an existing IP integrator design-related problem, use the IP Integrator Solution Center to guide you to the right information.


Vivado IP Integrator 2013.3 Known Issues

(Xilinx Answer 58074) 2013.3 - Vivado IP Integrator - Block design containing a MIG IP fails validation after upgrade to 2013.3
(Xilinx Answer 57370) 2013.3 - Vivado IP Integrator - System level connection recommendations for the VC709 with Dual DDR3 controller
(Xilinx Answer 58056) 2013.3 - Vivado IP Integrator - TCL script generated in 2013.2 is not setting the Microblaze IP configurations correctly
(Xilinx Answer 57882) 2013.3 - Vivado IP Integrator - Create, Import Peripheral Wizard generated IP is missing the Support Narrow Burst parameter on the AXI4 Master Interface
(Xilinx Answer 58119) 2013.3 - Vivado IP Integrator - Cannot assign external bus interface to AXI Slave on AXI APB bridge

Vivado IP Integrator 2013.2 Known Issues

(Xilinx Answer 56519) 2013.2 - Vivado IP Integrator - Interrupt sensitivity is not getting populated correctly in the IP Integrator Interrupt Controller customize GUI
(Xilinx Answer 55703) 2013.2 - Vivado IP Integrator - IRQ_F2P vector is not updating when connecting a vector port
(Xilinx Answer 56538) 2013.2 - Vivado IP Integrator - UART setting in XPS for a PS7 system are not preserved if Preset Import done to IPI-Zynq flows
(Xilinx Answer 56539) 2013.2 - Vivado IP Integrator - Bus interface property ID_WIDTH mis-match when using mig_7series connected to an AXI Interconnect
(Xilinx Answer 56584) 2013.2 - Vivado IP Integrator - Changing AXI protocol in Interface properties is not getting reflected in HDL wrapper
(Xilinx Answer 56587) 2013.2 - Vivado IP Integrator - READ/WRITE_OUTSTANDING parameter is not getting populated to the AXI_7Series MIG S_AXI port in Vivado IPI
(Xilinx Answer 56610) 2013.2 - Vivado IP Integrator - "ERROR [BD 41-237] Bus Interface property FREQ_HZ does not match between /mig_7series/S_AXI() and interconnect_1/s00_couplers/M_AXI()"
(Xilinx Answer 56611) 2013.2 - Vivado IP Integrator - "ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /mig_7series_1/S_AXI and /axi_interconnect/M_AXI"
(Xilinx Answer 56358) 2013.2 - Vivado IP Integrator - How can I import my Custom IP created in XPS CIP Wizard into IP Integrator?
(Xilinx Answer 56644) 2013.2 - Vivado IP Integrator - "[Project 1-486] Could not resolve non-primitive black box cell 'design1_mig_7series_1_0'" >
(Xilinx Answer 57091) 2013.2 - Vivado IP Integrator - Cannot generate Memory Test application after exporting IPI design to SDK
(Xilinx Answer 57111) 2013.2 - Vivado IP Integrator - Not able to associate ELF files directly in my IPI design
(Xilinx Answer 57168) 2013.2 - Vivado IP Integrator - Zynq AXI_PCIe - Errors out when assigning address to PCIE AXI BAR1



AR# 56612
日期 02/15/2016
状态 Active
Type 解决方案中心
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3