UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56777

LogiCORE IP DisplayPort v4.0 - GTH Common Block Refclk is not Connected Causing DRC Error

描述

When implementing a DisplayPort TX core (2.7G line rate, all default settings), the GTH common block have the GTREFCLK0 pin left floating. 

This causes the following DRC error in Vivado:

[Drc 23-20] Rule violation (REQP-45) must_use_ref_clock - displayport_0_tx_inst/inst/dport_tx_phy_inst/gth_wrapper_inst/gthe2_common_0_i: An input reference clock pin must be used.

解决方案

This issue will be fixed in the DisplayPort v4.1 core.

In the meantime, to work around the problem, follow the steps below:

  1. Navigate to <Project_directory>\.srcs\sources_1\ip\displayport_0\displayport_0\src   and then open <core_name>_gth_7_series_wrapper_4.v
     
  2. Find this line in the GTHE2_common instantiation:
      .GTREFCLK0                      (GT0_GTREFCLK0_COMMON_IN),
    Change it to:
      .GTREFCLK0                      (GT0_GTREFCLK0_IN),
  3. Reset your synthesis and implementation runs and the issue should now be resolved.


For a detailed list of Vivado LogiCORE IP DisplayPort Release Notes and Known Issues, see (Xilinx Answer 54522)

Revision History
7/17/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54522 LogiCORE IP DisplayPort -面向 Vivado 2013.1 和更新工具版本的版本说明和已知问题 N/A N/A
AR# 56777
日期 08/27/2014
状态 Archive
Type 综合文章
IP
  • DisplayPort
的页面