AR# 5678


Exemplar Spectrum: Read gives :hdl_file.v", line 14: Error, Empty port is not supported


Keywords: empty port, Exemplar, Spectrum, Read

Urgency: Standard

General Description:

After entering in my HDL code I try and do a 'Read' in Exemplar Spectrum. Eventually
it errors out and gives me an error message similar to the following:

"hdl_file.v", Error, Empty port is not supported
Error(s) found in Verilog source.

My design seems to run fine through other synthesis tools.


This may be due to an extra comma after a port declaration in the module declaration.
Apparantly Exemplar Spectrum does not allow an empty port, or no signal name, after
the comma, and errors out. The syntax creating the problem may look similiar to the

module test ( reset_l, clk, data_in1, data_in2

The empty port error in Exemplar would come from the place holder after the "checksignal"
comma, but no signal/port name is provided.

Removing the extra comma will fix this problem.
AR# 5678
日期 09/17/2002
状态 Archive
Type 综合文章
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