AR# 5682: FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design
FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design
Keywords: OBUF, OBUFE, OBUFT, 9500
General Description: After instantiating an OBUFE in an HDL design, FPGA Express will also place an OBUF after the OBUFE and cause multiple drivers errors during the Translate phase of implementation (NGDBUILD).
Infer the functionality of the OBUFE. For example:
VHDL: DOUT <= DATA when ENABLE='1' else 'Z';
Verilog: assign DOUT = ENABLE ? DATA : 1'bZ;
Instantiate an OBUFT and invert the signal that is used for the T pin.