How do I constrain a differential clock in Vivado?
Should I create a clock for each port (i.e. for the P and N side)?
What will happen if I create a clock on both the P and N side?
Also, do I need to constrain both the P and N sides of differential data ports in input delay and output delay constraints?
Only the P side of the differential ports needs to be constrained.
The tool will propagate the constraint forward to the output of the IBUFGDS instance.
If both are constrained, the tool will take them as two separate clock definitions and analyze inter clock paths between them.
This can lead to incorrect requirements.
Similarly, only the P-side of the differential data port needs to be constrained in the input delay and output delay constraints.
The analysis of the N-side path is exactly the same as the P-side.