AR# 5718: Virtex JTAG - How do I program multiple Virtex devices in a JTAG chain?
Virtex JTAG - How do I program multiple Virtex devices in a JTAG chain?
I am using multiple Virtex devices that are connected in a JTAG daisy-chain (the TDO of one device connects to the TDI of another device, all the TCKs are connected together as one TCK, and all the TMS pins are connected as one TMS pin).
Is it possible to configure this entire daisy chain via the Virtex JTAG pins?
Yes -- please utilize the following software and hardware procedures:
First, prepare the Virtex bit streams for JTAG configuration. For each bit stream in the Virtex daisy-chain, create the .bit file using the following command line:
bitgen -g startupclk:jtagclk designName.ncd
where "designName.ncd" is the name of the routed NCD file from PAR.
If you do not do this, the Virtex device will accept the bit stream, DONE and /INIT will both be High, but the device will not respond to stimulus. The above option instructs the Virtex device to use the clocks on the TCK pin to finish the JTAG configuration process.
If you do not wish to use the TCK to clock the start-up sequence, you must use the STARTUP_VIRTEX symbol to attach a specific internal clock net to be used for the start-up sequence. BitGen must then be instructed to use the USERCLK for start-up with the "g:userclk" option.
If you are configuring a Virtex device via JTAG only after power-up, you must set the mode pins of the Virtex device to 101 (M2=1, M1=0, M0=1 NOPULLUPS) or 001 (M2=0, M1=0, M0=1 PULLUPS). If you do not set the mode pins to 101 or 001 before power-up, and you then enter a configure instruction, the Virtex device may not configure reliably.
Now, place your bit files into the JTAG Programmer software to complete the configuration. (If you are using your own software, please read on.)
Configure the devices in the daisy-chain one at a time using the following steps:
1. Load the CFG_IN instruction into the first device (use BYPASS in all downstream devices).
2. Shift in the first bit stream with no leading zeros.
3. Go through the Test-Logic-Reset (TLR) process.
4. Load BYPASS in the first device and CFG_IN in the second device (use BYPASS in all downstream devices).
5. Shift in the second bit stream with 31 leading zeros.
6. Go through the TLR process.
Repeat steps 4 through 6 for each successive device, reducing the number of leading zeros by one for each device prior to the device being configured.
7. Load the JSTART command into all devices.
8. Go to Shift-DR and clock TCK twelve times.
All devices should be active at this point.
Troubleshooting the JTAG Configuration of an Individual Virtex Device
Note that the TAP is always active on Virtex devices and can be used for troubleshooting. In JTAG configuration mode, the DONE pin functions exactly as it does in non-JTAG configuration mode. While in JTAG configuration mode with Virtex, you may monitor DONE pin to see if the bit stream has been successfully loaded into the device.
If DONE is Low, three possible situations exist: the entire bit stream has not been sent, the entire bit stream has been sent but the start-up sequence has not finished, or an error has occurred. If the DONE pin goes High, this means that the Virtex device has received the entire bit stream and that the bit stream was not corrupted.
If the DONE pin has not gone High, the bit stream has been created with the "-g" option for JTAGCLK, and the JSTART instruction has been executed, it is possible that an error in the bit stream was detected. In the non-JTAG configuration of a Virtex device, this sort of failure is revealed via the /INIT pin. In Virtex JTAG configuration, the external /INIT pins are not used for reporting status, but it is possible to view the internal /INIT signal.
If you have finished a Virtex JTAG configuration and the DONE pin has stayed Low, you may check to see if an error was detected in the bit stream by following these steps:
1. Move the TAP to the test-logic-reset state.
2. Load the CFG_IN instruction.
3. Go to the Shift-DR state and shift in the following 64-bit pattern:
4. Load the CFG_OUT instruction.
5. Go to Shift-DR and clock TCK 32 times while reading TDO.
The data is the contents of the STATUS register. The last bit out will be a 1 if a CRC error occurred. After a successful configuration, the 32 bits would normally be:
The rightmost bit is the last one shifted out. If the returned values deviate from the above, a problem with your configuration may exist.