UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57338

MIG 7 Series DDR3 - VHDL ONLY - Designs fail during write calibration when the pin-out has a bank containing Addr/Cont groups in T0, T1, and T2 and a Data group in T3

描述

Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series DDR3 VHDL designs fail during write calibration when the pin-out has a bank containing Addr/Cont groups in T0, T1, and T2 byte lanes and a data group in byte lane T3.  This affects VHDL designs ONLY.  Identical MIG 7 series designs with the language set to Verilog will pass calibration successfully. 

When write calibration fails due to this issue, it fails with a late write pattern similar to XXXXFF00AA5555AA.  The expected Write Calibration pattern is FF00AA5555AA9966.

解决方案

This is an rtl issue with the assignment of the CTL_BYTE_LANE parameter calculation within the user_design/rtl/phy/mig_7series_v*_*_phy_top.vhd module.  The issue is the CTL_BYTE_LANE parameter calculation in the function CTL_BYTE_LANE_W does not consider byte group T2 when the number of Address/Control byte lanes is 3.  The evaluation of this calculation is different between the VHDL and Verilog RTL.  This issue is resolved in the attached patch.  Included in the patch are instructions on applying the patch to generated MIG 7 Series designs.

附件

文件名 文件大小 File Type
AR57338.zip 16 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 57338
日期 09/16/2013
状态 Active
Type 综合文章
器件
IP
的页面