AR# 57359


MIG Virtex-6 DDR3 - Generating a MIG DDR3 core targeting a single rank x8 RDIMM results in two sets of incorrectly generated CS and ODT signals


Virtex-6 MIG DDR3 designs targeting single rank x8 RDIMMs incorrectly included two sets of ODT and CS signals.

These parts only use one CS_n and one ODT. Manual modifications to the RTL and UCF are outlined in this answer record.



Version Fixed: Not to be Fixed. 

Please follow the below procedure to work around this limitation. The issue is present under ISE14.7 (v3.92)

To change the RTL to only include one CS_n pin and one ODT pin:

  1. Locate the nCS_PER_RANK top-level parameter in both the "example_design/rtl/ip_top/example_top.v" and "user_design/rtl/ip_top/core_name/.v" modules.
  2. Change the setting from 2 to 1 in both of these top-level files.

UCF Modifications

Locate the pin LOC for the "ddr3_cs_n[1]" pin and comment out the line. This pin is not needed for single rank RDIMM designs.



Answer Number 问答标题 问题版本 已解决问题的版本
50642 MIG Virtex-6 and Spartan-6 v3.92 - Release Notes and Known Issues for ISE Design Suite 14.3 N/A N/A
AR# 57359
日期 03/25/2016
状态 Active
Type 已知问题
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