AR# 57370


2013.3 Vivado IP Integrator - System level connection recommendations for the VC709 with Dual DDR3 controller


This answer record contains system level connection recommendations for the VC709 with Dual DDR3 controller.


Designing with Dual Memory Controller in VC709

Objective:  The VC709 board consists of 2 DDR3 SDRAM memories. This design example exploits the use of these 2 memories on board.

This design uses a single MIG configured for dual controller.

Facts to remember while designing with VC709 board:

  • The 2 memories are clocked by 2 different clock sources. One is the 200 MHz crystal which clocks the controller J1, while the 233 MHz crystal clocks the J3 controller for the 2nd Memory on board.
  • The REFCLK of J3 uses the SYSCLK of J1 since it is being driven at 200MHz. From the configurators perspective; REFCLK should be set to SYSCLK and whichever clock is driven at 200MHz; it simply assumes that SYSCLK and assigns it to REFCLK *.
  • The memory interconnect should be clocked by the ui_clk which is driven at lower crystal clock frequency. In our case; it would be 200MHz from controller J1 (c0 and not c1). *
  • From architecture perspective; the 2 controllers are clocked by 2 different clocks and hence belong to 2 different clock domains. Thus 2 separate resets each of which are provided by the MIG interfaces for J1 and J3 separately should be used. This would ensure no timing violations are encountered and that the design meets the timing requirements even though the clocking is from 2 different domains.
  • (100MHz) from c0(J1) ui_addnal_clk should be used to for clocking the fabric. Thus the proc_sys_rst of J1 should provide the fabric resets.
  • The proc_sys_rst blocks should use the respective mmcm_locked signals from the J3 (c1) and J1 (c0) controller.
  • In order to ensure that the timing of the design is met; it is important that the one proc_sys_rst which will be driven from the 100MHz clock (slowest_sync_clk) generated by c0 (J1) which is in sync with the 200MHz sysclk; in turn drives all the other fabric logic except the Master interface of J3.
    The other proc_sys_rst will be there to drive the c1_arestn and which will in turn be driven by the J3 233 MHz sysclk or c1_ui_clk. It will drive the c1_arestn of the MIG interface and the M01 (J3) aresetn port of the AXI memory interconnect
    * The tool automatically configures the MIG instance when selected for ddr3_sdram_socket_j1_j3

    Block Design:

Connections that require attention:

  • Connecting the Interconnect ACLK:
    The memory interconnect should be clocked by the lowest of MIG frequencies which being 200 MHz from the c0(J1) ui_clk. This connection is already handled by the board automation feature and the user does not need to modify it.

  • Connecting to the Master ports of the controller:
    Since the MIG has been configured for 2 controllers, the 2 interfaces will have their reset and clock signals. The M00 clock corresponds to J1 ui_clk (200MHz) and the M01 clock corresponds to the J3 ui_clk (233 MHz). They need to be connected accordingly from the ui_clk ports of the MIG.
    The M00 aresetn; should be connected to the reset output from J1s proc_sys_rst (peripheral_aresetn) and M01 aresetn to the the reset output from J3s proc_sys_rst (peripheral_aresetn), since these resets corresponds to their individual clock domains.
    The c0_aresetn and the c1_aresetn ports of the 2 MIG controllers respectively should also be connected to these resets.
AR# 57370
日期 10/30/2013
状态 Archive
Type 综合文章
People Also Viewed