AR# 57454


2013.2 Vivado HLS - Design with integer divider w/ operand widths greater than 64-bit fail SystemC RTL co-simulation


A design that uses a divider with input and/or output widths greater than 64-bit causes an assertion failure during SystemC co-simulation. 

The following message is issued:

Assertion failed: DIN0_WIDTH <= 64, file C:/Xilinx/Vivado_HLS/2013.2/common/technology/generic/SystemC/AESL_comp.h, line 877


The same design will pass Verilog and VHDL RTL co-simulations, export of IP-XACT succeeds, and RTL and post-implementation simulations can be successfully run in the Vivado tool using the VHLS generated project files.

As a result, RTL co-simulations can be used as a work-around.

Please bear in mind that the SystemC co-simulation uses simulation models, and the implementation tools use the RTL (Verilog or VHDL).

This issue will be fixed in Vivado HLS 2013.3.



Answer Number 问答标题 问题版本 已解决问题的版本
47429 Xilinx Vivado HLS Solution Center - Top Issues N/A N/A
AR# 57454
日期 10/20/2014
状态 Active
Type 已知问题
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