AR# 57662

MIG 7 Series AXI, ECC Enabled, 4:1 - dbg_rddata_r is half the width of dbg_rddata

描述

Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

For MIG 7 Series AXI, ECC Enabled, and 4:1 clock ratio designs, "dbg_rddata_r" is only half the width of "dbg_rddata". Therefore, when an ECC error occurs, half of the registered data is lost.

解决方案

To fix the issue, apply the following RTL changes to mig_7series_2_0_memc_ui_top_axi.v.

Change:

Line 960: reg [4*DQ_WIDTH-1:0]         dbg_rddata_r;

To:

Line 960:     reg [2*nCK_PER_CLK*DQ_WIDTH-1:0]         dbg_rddata_r;

Revision History
09/26/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 57662
日期 09/26/2013
状态 Active
Type 已知问题
器件
IP