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AR# 57756

MIG 7 Series DDR3 - tFAW timing parameter is set incorrectly for MT41J256m16XX-107 memory device

描述

Version Found: MIG 7 Series v2.0
Version Resolved: See (Xilinx Answer 54025)

MIG improperly set the tFAW timing parameter for the DDR3 part MT41J256m16XX-107 to 25ns. The correct setting is 35ns.

解决方案

To work around this issue until it is resolved within MIG, it is required that you manually modify the parameter.

  1. Open the "example_design/rtl/example_top.v" and the "user_design/rtl/core_name.v" modules.
  2. Locate the tFAW parameter.
  3. Modify the setting to 35ns.
  4. Re-implement the design.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 57756
日期 10/02/2013
状态 Active
Type 已知问题
器件
IP
的页面