AR# 57760

MIG 7 Series QDRII+ - Stage 1 calibration will always pass even if no edges are detected

描述

Version Found: v1.6
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series QDRII+ stage 1 calibration of read clock with respect to Q will always pass even if no edges are detected and the taps have maxed out. Only during Stage 2 calibration will failures be detected and cause calibration to stop.

解决方案

When debugging calibration failures, it is important to validate that stage 1 passed as expected using the enabled debug signals referenced in the 7 Series FPGAs Memory Interface Solutions v2.0 User Guide (UG586):
http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf

Revision History
10/01/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 57760
日期 10/01/2013
状态 Active
Type 已知问题
器件
IP