This answer record contains the Release Notes and Known Issues for the Video PHY Controller and includes the following:
Xilinx Forums:
General Information
Supported Devices can be found in the following three locations:
Subsystem or IP:
Linux Support
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version | IP Changelog | IP Patches | Software Driver Patches |
|---|---|---|---|---|
| v2.2(Rev 4) | 2019.2 | (Xilinx Answer 72923) | ||
| v2.2 (Rev 3) | 2019.1 | (Xilinx Answer 72242) | (Xilinx Answer 72731) | (Xilinx Answer 72475) - DisplayPort |
| v2.2 (Rev 2) | 2018.3 | (Xilinx Answer 71806) | (Xilinx Answer 71836) | |
| v2.2 (Rev 1) | 2018.2 | (Xilinx Answer 71212) | ||
| v2.2 | 2018.1 | (Xilinx Answer 70699) | ||
| v2.1 (Rev. 1) | 2017.4 | (Xilinx Answer 70386) | (Xilinx Answer 70174) | |
| v2.1 | 2017.3 | (Xilinx Answer 69903) | (Xilinx Answer 70174) | |
| v2.0 (Rev. 6) | 2017.2 | (Xilinx Answer 69326) | ||
| v2.0 (Rev. 5) | 2017.1 | (Xilinx Answer 69055) | ||
| v2.0 (Rev. 4) | 2016.4 | (Xilinx Answer 68369) | (Xilinx Answer 68685) - DisplayPort | |
| v2.0 (Rev. 3) | 2016.3 | (Xilinx Answer 68021) | ||
| v2.0 (Rev. 2) | 2016.2 | (Xilinx Answer 67345) | (Xilinx Answer 68151) | (Xilinx Answer 68152) - HDMI (Xilinx Answer 67924) - DisplayPort |
| v2.0 (Rev. 1) | 2016.1 | (Xilinx Answer 66930) | ||
| v2.0 | 2015.4 | (Xilinx Answer 66004) | (Xilinx Answer 66520) |
Known and Resolved Issues
The following tables 3 and 4 provides known issues for the Video PHY Controller LogiCORE IP, starting with v2.0, initially released in Vivado 2015.4.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 3: IP
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 72927) | When the 4th GT channel is enabled, the generated TMDS clock output is incorrect | v2.2 (Rev 2) | v2.2 (Rev 4) |
| (Xilinx Answer 72722) | DisplayPort - CPLL does not response after a series of plug/unplug or power on/off events | v2.2 (Rev 2) | v2.2 (Rev 3) |
| (Xilinx Answer 72322) | DisplayPort - The GT clocks TXOUTCLK and RXOUTCLK are incorrectly constrained by the tool | v2.2 (Rev 2) | v2.2(Rev 4) |
| (Xilinx Answer 70169) | Why does the HDMI RX Subsystem v3.0 fail when a design has both HDMI and DisplayPort subsystems? | v2.0 (Rev. 7) | v2.2 |
| (Xilinx Answer 69626) | Why do the settings reset to the defaults when updating the Vivado 2016.2 Video PHY Controller v2.0 (Rev. 2) to a later version? | v2.0 (Rev. 3) | v2.0 (Rev. 7) |
| (Xilinx Answer 68935) | Why does the Polarity Swapping register setting not seem to have any effect? | v2.0 (Rev. 5) | v2.0 (Rev. 6) |
| (Xilinx Answer 68781) | Why does it takes a long time to get the XVPHY_INTR_TXALIGNDONE event? | v2.0 (Rev. 4) | v2.0 (Rev. 5) |
| (Xilinx Answer 68431) | How do I use the DP159 forwarded clock for 1.62 Gbps for the Kintex UltraScale parts? | v2.0 | v2.0 (Rev. 5) |
| (Xilinx Answer 68156) | Why does the HDMI Receiver Subsystem fail HDCP authentication with some Samsung Blu-Ray Players? | v2.0 | v2.0 (Rev. 4) |
| (Xilinx Answer 67966) | Transceiver width gets ignored when the RX/TX protocol type gets changed from DisplayPort to None when using a Tcl script to instance the IP in Block Design | v2.0 | v2.0 (Rev. 5) |
| (Xilinx Answer 66989) | Why do I get critical warning on GT placement when multiple Video PHY Controllers are used in different Block Designs? | v2.0 | v2.0 (Rev. 3) |
| (Xilinx Answer 66691) | Why do I get a critical warning about parts of the NI-DRU being redefined when using UHD-SDI XAPPs and the HDMI RX Subsystem with the Video PHY Controller in the same design? | v2.0 | N/A |
| (Xilinx Answer 66538) | Why does the Video PHY Controller throw an error and fail to generate when selecting a HDMI TX or HDMI RX only configuration? | v2.0 | v2.0 (Rev. 1) |
| (Xilinx Answer 66537) | How do I modify the output of the Video PHY for my design, if the output is encrypted when generating and HDMI PHY for the 7 Series GTX? | v2.0 | v2.0 (Rev. 1) |
Table 4: Software Driver
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 72545) | DisplayPort 1.4 TX Subsystem - Is it required to enable TX buffer bypass for DP1.4 PHY compliance? | ||
| (Xilinx Answer 72476) | DisplayPort 1.4 RX Subsystem - Why does the core fail to train at 8.1 Gbps on GTYE4 when DOWNSPREAD is enabled? | v2.2 (Rev. 3) | N/A |
| (Xilinx Answer 69562) | 2017.3 - Changes to the DRP Read API | v2.1 | N/A |
| (Xilinx Answer 66545) | Why do I see link quality issues at 4Kp60 for a HDMI Receiver using 7 Series GTX? | v2.0 | v2.0 (Rev. 1) |
| Revision History: | |
|---|---|
| 10/04/2019 | Added (Xilinx Answer 72927) and (Xilinx Answer 72722) to IP known issue table, Patch (Xilinx Answer 72731) and (Xilinx Answer 71836) to version table |
| 07/12/2019 | Added (Xilinx Answer 72545) to General Guidance Table |
| 06/24/2019 | Added (Xilinx Answer 72475) to the version table and (Xilinx Answer 72476) to the known issues table |
| 05/08/2019 | Added (Xilinx Answer 72322) to the known issues table |
| 04/09/2018 | Added (Xilinx Answer 69562) |
| 04/04/2018 | Added v2.1 (Rev. 1) and v2.2 to Version Table |
| 11/20/2017 | Added (Xilinx Answer 70169), (Xilinx Answer 70174) and updated resolved issues. |
| 10/04/2017 | Added v2.1 to Version Table |
| 08/16/2017 | Added v2.0 (Rev. 6) to Version Table and (Xilinx Answer 69626) |
| 04/05/2017 | Added v2.0 (Rev. 5) to Version Table and (Xilinx Answer 68935) |
| 02/27/2017 | Added (Xilinx Answer 68781) |
| 02/07/2017 | Added (Xilinx Answer 68431) |
| 12/14/2016 | Added v2.0 (Rev. 2), v2.0 (Rev. 3) and v2.0 (Rev. 4) to Version Table and (Xilinx Answer 68156), (Xilinx Answer 66520), (Xilinx Answer 68151), (Xilinx Answer 68152) and (Xilinx Answer 67924) |
| 09/29/2016 | Added (Xilinx Answer 67966) |
| 04/18/2016 | Added (Xilinx Answer 66989) |
| 04/06/2016 | Added v2.0 (Rev. 1) to Version Table |
| 02/23/2016 | Added (Xilinx Answer 66537), (Xilinx Answer 66538), (Xilinx Answer 66545), and (Xilinx Answer 66691) |
| 11/24/2015 | Initial Release |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 56852 | Xilinx Multimedia, Video and Imaging Solution Center - Top Issues | N/A | N/A |
| 54522 | LogiCORE IP DisplayPort -面向 Vivado 2013.1 和更新工具版本的版本说明和已知问题 | N/A | N/A |
| AR# 57842 | |
|---|---|
| 日期 | 01/20/2020 |
| 状态 | Active |
| Type | 版本说明 |
| IP | |