AR# 57868

MIG 7 Series RLDRAM3 - memory controller hangs when write command then read command are issued to address 0


Version Found: v1.9.a
Version Resolved: See (Xilinx Answer 54025)

After calibration, the memory controller state machine inside mig_7series_v1_9_rld_mc.v can hang when issuing a write and then read command to address 0. This only occurs on address 0 immediately after calibration as a result of the "addr_check" comparison logic checking irrespective of the command type (i.e., WRITE, READ, NOP).


The "addr_match" signal needs to be qualified with an additional signal before assertion to prevent the memory controller from hanging. The attached files mig_7series_v1_9_rld_mc.v and mig_7series_v2_0_rld_mc.v use "prev_wr_addr_valid" to qualify "addr_match" and can drop-in replace the existing file in the ./user_design/rtl/controller/ directory. Please refer to the readme.txt for instructions for installing each patch.

Revision History
06/19/2013 - Initial release


文件名 文件大小 File Type 17 KB ZIP 17 KB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 57868
日期 10/21/2013
状态 Active
Type 已知问题