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AR# 5791

FPGA Express 3.2 - Verilog pre-processor available to allow 'ifdef, 'else, and 'endif


Keywords: Verilog, FPGA Express, 'ifdef, 'else, 'endif, pre-processor

Urgency: Standard

General Description:
FPGA Express 3.2 now has a Verilog Pre-processor that allows the use of the following directives:

`define macros with and without arguments

This pre-processor is not enabled automatically, so users will have to set a switch to turn it on.
It is not turned on by default because when it is on, it will ignore the //synopsys translate_off
compiler directive.


To enable this feature, select Synthesis -> Options and set the proper option.

In standalone FPGA Express, check the box next to:
"Enable Verilog Pre-processor"

In the Foundation Project Manager, select "Enable" under the option:
"Verilog 'ifdef support"

In Foundation ISE, right-click on 'Synthesize' and select properties.
Click on the box next to 'Enable Verilog Preprocessor'.

In the fe_shell, open your project and set the environment variable:

fe_shell>open_project my_project.exp
fe_shell>set proj_enable_vpp yes
AR# 5791
日期 08/11/2003
状态 Archive
Type 综合文章