AR# 58057


MIG 7 Series - IES and VCS Simulator Support


MIG 7 Series v2.0 Rev1 IP now supports IES and VCS simulations for Verilog designs only and simulations must be run stand-alone outside of the Vivado tool.


The scripts attached at the end of this answer record are targeted for the MIG 7 Series IP example design generated by running "Open IP Example Design" in the Vivado GUI. Any simulations of the User Design or custom designs will require the user to create their own scripts for simulations.

Steps for running the simulations scripts can be located in the readme.txt file inside the attachment.
Note: QDRII+ memory models are required for simulations and must be obtained directly from the memory vendor.

For LPDDR2 simulations, the following error message will occur using VCS:

Error-[SE] Syntax error
Following verilog source has syntax error :
"../../user_design/rtl/controller/mig_7series_v2_0_arb_select.v", 402 token is '*)'

To remove this error message, the above line 'always @(/*AS*/*)' should be replaced with 'always @(*)' in the file mig_7series_v2_0_arb_select.v.

Revision History
10/25/2013 - Initial release


文件名 文件大小 File Type 26 KB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
51178 Xilinx MIG 7 Series Design Assistant - Simulating a MIG DDR3 example design using VCS N/A N/A
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 58057
日期 11/22/2013
状态 Active
Type 综合文章
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