AR# 58158

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LogiCORE IP AXI Video Direct Memory Access - Core not transferring data when used in a processor-less IPI system

描述

I had a working design in XPS and I am now trying to port that over to IPI in Vivado. The design did not have a processor, but rather used XPS to stitch all my cores together. Of particular interest, I have an AXI VDMA that talks through an AXI Interconnect to MIG.

When I set up the same system using IPI, errors occur in the status register (0x4041) and there is data not being transferred properly to or from memory.

What is the problem?

解决方案

Vivado IPI contains additional DRC checks when designing the block diagram. Namely, IPI strongly urges you to assign address space to MIG, even when it is only being driven by the VDMA. Previously, XPS would simply assign 0x0 as the base address for all the masters by default and the Interconnect would pass requests through successfully since there was only the one bus master. However, the IPI does not assign such a default address and will communicate this to you through a warning message.

To solve this problem, assign the proper addresses to MIG in the IPI design.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54448 LogiCORE IP AXI Video Direct Memory Access - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 58158
日期 11/05/2013
状态 Archive
Type 综合文章
IP
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