I had a working design in XPS and I am now trying to port that over to IPI in Vivado. The design did not have a processor, but rather used XPS to stitch all my cores together. Of particular interest, I have an AXI VDMA that talks through an AXI Interconnect to MIG.
When I set up the same system using IPI, errors occur in the status register (0x4041) and there is data not being transferred properly to or from memory.
What is the problem?
Vivado IPI contains additional DRC checks when designing the block diagram. Namely, IPI strongly urges you to assign address space to MIG, even when it is only being driven by the VDMA. Previously, XPS would simply assign 0x0 as the base address for all the masters by default and the Interconnect would pass requests through successfully since there was only the one bus master. However, the IPI does not assign such a default address and will communicate this to you through a warning message.
To solve this problem, assign the proper addresses to MIG in the IPI design.