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AR# 58241

2013.3 Vivado IP Integrator - MIG block diagram does not get properly updated after recustomization


Version Found: v2.0 Rev1
Version Resolved: See (Xilinx Answer 54025)

After adding the MIG IP and customizing the core into the IP Integrator block diagram, customization changes take affect correctly (i.e. data width is set to 16 bits).

However, any additional re-customization of the MIG IP will not be reflected in the IP Integrator Block Diagram.

For example, if you change the data width from 16 to 32 bits the block diagram will still show only 16 bits for data.


If re-customization of the MIG IP block is required, the following Tcl commands must be entered into the Tcl console after re-customization is complete:

set_property -name {CONFIG.XML_INPUT_FILE} -value  {} -objects [get_bd_cells mig_7series_0]; 
set_property -name {CONFIG.XML_INPUT_FILE} -value  {mig_a.prj} -objects [get_bd_cells mig_7series_0]

This issue is fixed starting in Vivado 2013.4.



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 58241
日期 09/24/2014
状态 Archive
Type 综合文章
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series