Version Found: 2.2 (PG023)
Version Resolved and other Known Issues: See (Xilinx Answer 47441) for v1.7, (Xilinx Answer 54645) for v2.2
The "Legacy Interrupt Mode" section in (PG023) Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 core is not correct.
By following the instructions provided, the root receives two INTA_ASSERT/DEASSERT pairs, and cfg_interrupt_sent is asserted four times instead of only twice for INTA_ASSERT and INTA_DEASSERT sent.
This is a known issue in the (PG023) Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 core document. This will be fixed in a future release of the document.
To correctly generate the Legacy Interrupt, follow the steps below:
- The User Application first asserts cfg_interrupt_int and cfg_interrupt_pending to assert the interrupt.
- The core then asserts cfg_interrupt_sent to indicate that the interrupt is accepted.
On the following clock cycle, the User Application deasserts cfg_interrupt_int and, if the Interrupt Disable bit in the PCI Command register is set to 0, the core sends and asserts the interrupt message (Assert_INTA).
- After the User Application deasserts cfg_interrupt_int, the core sends a deassert interrupt message (Deassert_INTA).
This is indicated by the assertion of cfg_interrupt_sent for the second time.
- cfg_interrupt_int must be asserted until the user application receives confirmation of Assert_INTA, which is indicated by the assertion of cfg_interrupt_sent.
Deasserting cfg_interrupt_int causes the core to send Deassert_INTA.
cfg_interrupt_pending must be asserted until the interrupt has been serviced, or the interrupt status bit in the status register is not updated correctly.
If the software reads this bit, it detects no interrupt pending.
11/07/2013 - Initial release