AR# 58307


MIG 7series - IPI block design Interrupt signal direction is incorrect


Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)

With ECC enabled, MIG has a signal named Interrupt which should be output as per UG586

However, in the IPI GUI the Interrupt signal is incorrectly defined as an input which prevents users from connecting the interrupt to the IRQ_F2P input of ZYNQ.


This issue only arises with IPI designs.

As the RTL is correct, you can work around this by packaging the IP catalogue MIG and bringing it into IPI as a custom IP. 

Another option is to edit the <project>.srcs/sources_1/bd/<block diagram>/ip/<block diagram>_mig_7series_0_0/<block diagram>_mig_7series_0_0.xml file and change the lines below:








The interrupt input will then change to an output in the GUI.

Revision History

11/24/2014 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 58307
日期 11/26/2014
状态 Active
Type 已知问题
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