UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58402

SRIO GEN2 v3.0 and earlier - Update to 7 Series GTX Transceiver Port RXDFEXYDEN

描述

By default, the SRIO core uses DFE mode.

For DFE mode, it is recommended to update RXDFEXYDEN to '1'. This change enhances performance for medium and long reach applications with channel losses of 15 dB or higher at the Nyquist frequency.

For more information on this change, see (Xilinx Answer 58244) Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode.

解决方案

In gt_wrapper_gt_<core_name>.v/vhd, the RXDFEXYDEN port should be changed from '0' to '1'.

This will be updated in the future versions of the IP cores.


Revision History
11/22/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58244 7 系列 FPGA GTX 收发器的设计咨询 - DFE 模式下的 RXDFEXYDEN 端口更新 N/A N/A
AR# 58402
日期 11/22/2013
状态 Active
Type 综合文章
IP
  • Serial RapidIO
的页面