AR# 58435


MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the DDR4, DDR3, QDRII+, QDRIV, RLDRAM3, LPDDR3 UltraScale and UltraScale+ Cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the programmable logic memory interface IP cores supported in UltraScale and UltraScale+ based devices.

Memory IP Page:


Xilinx Forums:

Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

DDR4 VersionDDR3 VersionRLDRAM3 VersionQDRII+ VersionQDRIV VersionLPDDR3 VersionVivado Tools Version
v2.2 (Rev. 10)v1.4 (Rev. 10)v1.4 (Rev. 10)v1.4 (Rev. 10)v2.0 (Rev. 10)v1.0 (Rev. 10)2020.2
v2.2 (Rev. 9)v1.4 (Rev. 9)v1.4 (Rev. 9)v1.4 (Rev. 9)v2.0 (Rev. 9)v1.0 (Rev. 9)2020.1
v2.2 (Rev. 8)v1.4 (Rev. 8)v1.4 (Rev. 8)v1.4 (Rev. 8)v2.0 (Rev. 8)v1.0 (Rev. 8)2019.2
v2.2 (Rev. 7)v1.4 (Rev. 7)v1.4 (Rev. 7)v1.4 (Rev. 7)v2.0 (Rev. 7)v1.0 (Rev. 7)2019.1
v2.2 (Rev. 6)v1.4 (Rev. 6)v1.4 (Rev. 6)v1.4 (Rev. 6)v2.0 (Rev. 6)v1.0 (Rev. 6)2018.3
v2.2 (Rev. 5)v1.4 (Rev. 5)v1.4 (Rev. 5)v1.4 (Rev. 5)v2.0 (Rev. 5)v1.0 (Rev. 5)2018.2
v2.2 (Rev. 4)v1.4 (Rev. 4)v1.4 (Rev. 4)v1.4 (Rev. 4)v2.0 (Rev. 4)v1.0 (Rev. 4)2018.1
v2.2 (Rev. 3)v1.4 (Rev. 3)v1.4 (Rev. 3)v1.4 (Rev. 3)v2.0 (Rev. 3)v1.0 (Rev. 3)2017.4
v2.2 (Rev. 2)v1.4 (Rev. 2)v1.4 (Rev. 2)v1.4 (Rev. 2)v2.0 (Rev. 2)v1.0 (Rev. 2)2017.3
v2.2 (Rev. 1)v1.4 (Rev. 1)v1.4 (Rev. 1)v1.4 (Rev. 1)v2.0 (Rev. 1)v1.0 (Rev. 1)2017.2
v2.1 (Rev. 1)v1.3 (Rev. 1)v1.3 (Rev. 1)v1.3 (Rev. 1)v1.2 (Rev. 1) 2016.4
v2.1v1.3v1.3v1.3v1.2 2016.3
v2.0 (Rev. 1)v1.2 (Rev. 1)v1.2 (Rev. 1)v1.2 (Rev. 1)v1.1 (Rev. 1) 2016.2
v2.0v1.2v1.2v1.2v1.1 2016.1
v1.1v1.1v1.1v1.1v1.0 2015.4
v1.0v1.0v1.0v1.0  2015.3
v7.1v7.1v7.1v7.1  2015.2
v7.0v7.0v7.0v7.0  2015.1
v6.1v6.1v6.1v6.1  2014.4
v6.0v6.0v6.0v6.0  2014.3
v5.0 (Rev. 1)v5.0 (Rev. 1)v5.0 (Rev. 1)v5.0 (Rev. 1)  2014.2
v5.0v5.0v5.0v5.0  2014.1


Starting with the release of Vivado 2015.3 the MIG wizard is no longer used.

A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Table 2 provides answer records for general guidance when using UltraScale family external memory interface IP.

Table 2: General Guidance and Design Advisories

Answer RecordTitle
(Xilinx Answer 59625)MIG UltraScale - Design Methodology Checklist
(Xilinx Answer 61304)MIG UltraScale - Clocking Guidelines and Requirements
(Xilinx Answer 68937)MIG UltraScale DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide
(Xilinx Answer 71119)UltraScale/UltraScale+ Memory IP - Reading and Understanding the Calibration Margins Reported in the MIG Dashboard
(Xilinx Answer 63462)MIG UltraScale - Sample CSV data file for creating Custom Parts
(Xilinx Answer 63831)MIG UltraScale - Migrating and Upgrading IP into 2015.1
(Xilinx Answer 61598)Design Advisory Master Answer Record for Kintex UltraScale FPGA
(Xilinx Answer 61930)Design Advisory Master Answer Record for Virtex UltraScale FPGA
(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements
(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs
(Xilinx Answer 73068)Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions May Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardware
(Xilinx Answer 76121)UltraScale/UltraScale+ and Zynq MPSoC DDR Memory Interface IP - PCB Simulation Support

Known and Resolved Issues

Table 3 provides a list of the individual release notes and known issue answer records for each UltraScale family external memory interface IP.

Table 3: UltraScale Family External Memory IP Release Notes and Known Issues Answer Records

Answer RecordTitle
(Xilinx Answer 69035)UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues
(Xilinx Answer 69036)UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues
(Xilinx Answer 69037)UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues
(Xilinx Answer 69038)UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues
(Xilinx Answer 69039)UltraScale/UltraScale+ QDRIV - Release Notes and Known Issues
(Xilinx Answer 69040)UltraScale/UltraScale+ LPDDR3 - Release Notes and Known Issues


Table 4 provides a list of known and resolved issues that apply to all UltraScale family external memory interface IP.

Table 4: Known and Resolved Issues

Answer RecordTitleVersion
(Xilinx Answer 76121)UltraScale/UltraScale+ and Zynq MPSoC DDR Memory Interface IP - PCB Simulation Support ArticleNABNAB
(Xilinx Answer 75986)UltraScale/UltraScale+ DDR4 IP - Multi Rank DIMM Designs Fail Calibration on the Second Rank in 2020.22020.22020.2.1
(Xilinx Answer 73715)UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Later2020.1NF
(Xilinx Answer 73714)UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware2020.1NF
(Xilinx Answer 73461)UltraScale/UltraScale+ DDR3/DDR4 IP - Implemented design shows Memdata errors due to improperly or nonexistent instantiated BRAM and will not calibratev2.2 (Rev. 6)v2.2 (Rev. 10)
(Xilinx Answer 73068)Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions May Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardware2016.42020.1
(Xilinx Answer 72582)UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 252019.12020.1
(Xilinx Answer 72044)UltraScale/UltraScale+ Memory IP - Default Vivado Simulation Behavior Change in 2018.2 and Later Versions2018.22020.1
(Xilinx Answer 69947)UltraScale Memory IP - designs giving hold violations2017.1Not Resolved
(Xilinx Answer 69827)UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces2017.22017.3
(Xilinx Answer 69611)UltraScale/UltraScale+ Memory IP - Example Design - Advanced Traffic Generator (ATG) usage related data compare errors2014.1NAB
(Xilinx Answer 69324)UltraScale+ MPSoC Memory IP - The SFVC784 package has incorrect data rates in PL Memory Interfaces2017.12017.2
(Xilinx Answer 69291)UltraScale+ MPSoC Memory IP - The SFVA625 package does not support PL Memory Interfaces2017.12017.2
(Xilinx Answer 68976)UltraScale/UltraScale+ Memory IP - User addition of pblock might cause skew violations between RIU_CLK and PLL_CLK pins of BITSLICE_CONTROL2015.3Not Resolved
(Xilinx Answer 67392)UltraScale/UltraScale+ Memory IP - pulse width violations can occur2016.22017.1
(Xilinx Answer 67967)UltraScale/UltraScale+ Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency range2016.32016.4
(Xilinx Answer 67957)UltraScale/UltraScale+ Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IP2016.32016.4
(Xilinx Answer 67933)UltraScale/UltraScale+ Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part2016.32017.1
(Xilinx Answer 68028)UltraScale/UltraScale+ Memory IP - Pulse width violations occur for designs that violate the maximum BUFGCE timing spec with the Reference Input Clock Speed (ps)2016.32017.1
(Xilinx Answer 67684)UltraScale/UltraScale+ Memory IP - moving IP that uses custom memory parts (CSV) might cause problems2016.22016.3
(Xilinx Answer 67335)UltraScale/UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skipped2016.22016.3
(Xilinx Answer 66951)UltraScale/UltraScale+ Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check2016.12016.3
(Xilinx Answer 66360)UltraScale/UltraScale+ Memory IP - Core Container does not include *.csv file when a custom memory part is created2015.32016.3
(Xilinx Answer 67225)UltraScale/UltraScale+ Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IP2016.12016.3
(Xilinx Answer 67224)UltraScale/UltraScale+ Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCM2016.12016.2
(Xilinx Answer 67164)UltraScale+ Memory IP - timing failures occur due to high congestion levels2016.2NF
(Xilinx Answer 66800)UltraScale Memory IP - When the reset_n pin is located in a bank with an I/O Standard that has an incompatible voltage level the following error is seen during 'opt_design': [Mig 66-99]2016.1NF
(Xilinx Answer 59990)UltraScale/UltraScale+ Memory IP - IPI MIG simulation does not have memory models available2016.3NF
(Xilinx Answer 66678)UltraScale/UltraScale+ Memory IP - Design fails during 'opt_design' when using Custom CSV2015.22016.1
(Xilinx Answer 65431)UltraScale/UltraScale+ Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraint2015.32016.1
(Xilinx Answer 62543)UltraScale/UltraScale+ Memory IP - Certain speed grades incorrectly prevent previously allowed input clock periods2014.32016.1
(Xilinx Answer 65370)UltraScale/UltraScale+ Memory IP - pblocks containing Memory IP logic must be contained within the same clock region the memory I/O is located in2015.32015.4
(Xilinx Answer 65327)UltraScale/UltraScale+ Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting it.2015.32015.4
(Xilinx Answer 64778)UltraScale/UltraScale+ Memory IP - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bank2015.12015.4
(Xilinx Answer 64188)UltraScale/UltraScale+ Memory IP - sys_rst missing set_false_path constraint2015.12015.4
(Xilinx Answer 64071)UltraScale/UltraScale+ Memory IP - Custom Memory Parts Fail Simulation2015.12015.3
(Xilinx Answer 64923)UltraScale/UltraScale+ Memory IP - Hardware Manager Xicom error messages occurring after programming device2015.12016.3
(Xilinx Answer 64069)UltraScale/UltraScale+ Memory IP - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pins2015.12015.2
(Xilinx Answer 64431)UltraScale/UltraScale+ Memory IP - [Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 02014.42015.1
(Xilinx Answer 62774)UltraScale/UltraScale+ Memory IP - timing failures may be seen with MIG generated example design2014.42015.1
(Xilinx Answer 64070)UltraScale/UltraScale+ Memory IP - Designs with multiple controllers might generate ERROR::34 message2014.42015.1
(Xilinx Answer 62649)UltraScale/UltraScale+ Memory IP - GUI allows core generation even if all address and control byte lanes have not been selected2014.32015.1
(Xilinx Answer 59989)UltraScale/UltraScale+ Memory IP - Critical warnings are generated when multiple MIG instances are included in a design2014.12015.1
(Xilinx Answer 59991)UltraScale/UltraScale+ Memory IP - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful2014.12015.1
(Xilinx Answer 61696)UltraScale/UltraScale+ Memory IP - The funcsim.v/.vhdl structural simulation model is not supported2014.2NF
(Xilinx Answer 61076)UltraScale/UltraScale+ Memory IP - Multiple instances of MIG IP fails with "[Place 30-678] Failed to do clock region partitioning"2014.22014.3
(Xilinx Answer 60953)UltraScale/UltraScale+ Memory IP - Output Products must be generated before opening the IP Example Design2014.22014.3
(Xilinx Answer 64410)UltraScale/UltraScale+ Memory IP - Can either external or internal VREF be used?2014.1NAB

Revision History:
04/16/2014Initial release
06/04/2014Updated for 2014.2
10/01/2014Updated for 2014.3
10/16/2014Added link to Hardware Debug Guide
11/07/2014Updated for 2014.4
12/16/2014Added AR62930
01/08/2015Added AR63261
04/15/2015Updated for 2015.1 release
06/24/2015Updated for 2015.2 release
07/06/2015Added AR64887
07/09/2015Added 64923
08/07/2015Added 64946
09/30/2015Updated for 2015.3
11/24/2015Updated for 2015.4
01/26/2015Added 66471
04/13/2016Updated for 2016.1 release
09/19/2016Added 67891
10/05/2016Updated for 2016.3 release
02/08/2017Added 61598, 61930, 62483, 64856, 68169
03/24/2017Updated for 2017.1 release, Added LPDDR3, Added 66471, 67979, 67956, 68894, 68895, 68843
04/18/2017Created Answer Records for Each Memory Controller Type
06/05/2017Updated for 2017.2
07/31/2017Updated debugging link to AR#68937
12/13/2017Updated formatting and updated for 2017.4
03/14/2018Updated for 2018.1 and added 71119
09/20/2018Updated for 2018.3
05/02/2019Updated for 2019.1
08/23/2019Added AR 72044
08/27/2019Added AR 72582
10/20/2019Updated for 2019.2
03/26/2020Added DAAR 73068
05/21/2020Added AR73714, Added AR73715; Updated for 2020.1
09/30/2020Updated AR72044 as resolved
01/08/2121Updated for 2020.2; Added AR#75986
02/05/2021Added AR#73461
03/02/2021Added AR#76121




AR# 58435
日期 03/31/2021
状态 Active
Type 版本说明
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