描述

解决方案

The ZC702 Rev 1.1 changes are listed below:

• Replaced U61 TXS02612 SDIO level shifter with internal pull-ups with Maxim level shifter
• Added series resistor 40 - 60 ohm resistor near the FPGA on the SDIO CLK trace MIO40 (E14)
• Added parallel 100 ohm DNP pull-up and pull-down termination to the SDIO CLK trace MIO40 (E14), near the level shifter
• DNP the CMD line 4.7 k pull-up on the SD level shifter
• Removed 4.7 k pull-down on CKE; replaced with 40 ohm resistor to VTTDDR_PS, place termination in middle of 4 components (same T-branch topology as address / CTRL termination)
• Changed the timing on the release of SRST_B and POR_B by changing capacitor values on Voltage Supervisor U2 (MAX16025).  Set SRST_B to 35 us delay, set POR_B to 13.2 ms delay
• Moved VCC4A_PG signal to controller ADDR53 with VADJ
• Add "PG C2M" label near DS24 on the silkscreen
• Added 0 ohm and DNP resistor to Pins 2 and DNP to Pin 14 of Micron QSPI footprint, for Spansion QSPI support
• Updated USB power / GND traces
• Changed USB ULPI and UART differential P/N data traces to 90 ohms impedance
• Removed R29, R30, R46, R47 resistors
• Added +/- 50 mils length match requirement to QSPI interface
• Changed C221 to a 0402 0 ohm resistor
• Added 2 0.47 uF capacitors, named the VCCPLL net after the L6 filter bead

Decoupling changes:

• ZC702 PL VCCINT: changed to 330 uF (1), 4.7 uF (5), 0.47 uF (7)
• ZC702 PL VCCBRAM: changed to 100 uF (1), 4.7 uF (2), 0.47 uF (3)
• ZC702 PL VCCAUX: changed to 47 uF (1), 4.7 uF (2), 0.47 uF (4)
• ZC702 PL VCCO: changed to 47 uF (1), 4.7 uF (3), 0.47 uF (5)

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