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AR# 58479

Zynq-7000 SoC ZC706 评估套件 - 从 rev 1.1 至 rev 1.2

描述

ZC706 评估套件 rev 1.1 和 PCB 1.2 间有什么改动?

解决方案

ZC706 Rev 1.2 变化如下:

  • 在VCCPLL上加 2 个 0.47uF 的电容,同时命名 VCCPLL 网络
  • 在所有 DDR3 和 MIO 网络上更新包延迟

UG933 更新导致长度匹配调整:

  • ULPI_Group: +/- 100 ps centered on clock: USB_CLKOUT, USB_DATA0, USB_DATA1, USB_DATA2, USB_DATA3, USB_DATA4, USB_DATA5, USB_DATA6, USB_DATA7, USB_DIR, USB_NXT, USB_STP
  • RGMII_TX_Group: +/- 100 ps centered on clock: PHY_TXD0, PHY_TXD1, PHY_TXD2, PHY_TXD3, PHY_TX_CLK, PHY_TX_CTRL
  • RGMII_RX_Group: +/- 100 ps centered on clock: PHY_RXD0, PHY_RXD1, PHY_RXD2, PHY_RXD3, PHY_RX_CLK, PHY_RX_CTRL
  • SDIO_LS_Group: +/- 100 ps centered on clock: SDIO_CD_DAT3_LS, SDIO_CLK_LS, SDIO_CMD_LS, SDIO_DAT0_LS, SDIO_DAT1_LS, SDIO_DAT2_LS
  • SDIO_Conn_Group: +/- 100 ps centered on clock: SDIO_CD_DAT3, SDIO_CLK, SDIO_CMD, SDIO_DAT0, SDIO_DAT1, SDIO_DAT2
  • QSPI_Group: +/- 100 ps centered on clock: QSPI_CLK, QSPI_CS_B, QSPI_IO0, QSPI_IO1, QSPI_IO2, QSPI_IO3

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AR# 58479
日期 05/28/2018
状态 Active
Type 综合文章
Boards & Kits
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