Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 54645)
If simulating the example design for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 core generated with 250 MHz reference clock and PIPE simulation enabled, the simulation stops after the following message:
"System Reset is De-asserted...".
This is a known issue to be fixed in a future release of the core.
To work around this issue, replace the generated files with the ones attached at the end of this answer record.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
12/09/2013 - Initial release