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AR# 5894

Virtex Timing - What is the CLKA -> CLKB setup time for different ports (Tbccs) timing parameter?


In the Virtex data sheets, what does the block RAM timing parameter "CLKA -> CLKB setup time for different ports (Tbccs)" actually mean?


Suppose you are using dual-port block RAM where both clocks are completely independent of each other. The design requires a WRITE on one port and a READ from the same address on the other port.

This timing parameter (Tbccs) is the minimum amount of time required between the two clock edges to guarantee the correct data will appear on DOUT.

AR# 5894
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章