描述

In the Virtex data sheets, what does the block RAM timing parameter "CLKA -> CLKB setup time for different ports (Tbccs)" actually mean?

解决方案

Suppose you are using dual-port block RAM where both clocks are completely independent of each other. The design requires a WRITE on one port and a READ from the same address on the other port.

This timing parameter (Tbccs) is the minimum amount of time required between the two clock edges to guarantee the correct data will appear on DOUT.