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AR# 59288

LogiCORE DisplayPort v4.2 - Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11?

描述

Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11 from the DisplayPort Product Guide (PG064), December 18, 2013?

解决方案

In a case which was reported, it was found that in order for the PHY to reliably return from reset, the following steps were required:

  1. Set PHY_RESET register to 0x03 (reset both CPLL and GT RX/TX).
  2. Set PHY_RESET register to 0x02 (release CPLL reset only).
  3. Wait until all lane CPLLs have locked (both bits 5:4 in PHY_STATUS register set to '1').
  4. Set PHY_RESET register to 0x00 (all resets released = inactive).
  5. Wait until also the "Reset Done" flags have activated (PHY_STATUS = 0xFF).

 

This will be updated in the next release of the LogiCORE DisplayPort Product Guide.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54522 LogiCORE IP DisplayPort -面向 Vivado 2013.1 和更新工具版本的版本说明和已知问题 N/A N/A
AR# 59288
日期 05/12/2014
状态 Archive
Type 综合文章
器件
  • Kintex-7
IP
  • DisplayPort
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