Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11 from the DisplayPort Product Guide (PG064), December 18, 2013?
In a case which was reported, it was found that in order for the PHY to reliably return from reset, the following steps were required:
- Set PHY_RESET register to 0x03 (reset both CPLL and GT RX/TX).
- Set PHY_RESET register to 0x02 (release CPLL reset only).
- Wait until all lane CPLLs have locked (both bits 5:4 in PHY_STATUS register set to '1').
- Set PHY_RESET register to 0x00 (all resets released = inactive).
- Wait until also the "Reset Done" flags have activated (PHY_STATUS = 0xFF).
This will be updated in the next release of the LogiCORE DisplayPort Product Guide.