General Description: When implementing a Virtex design that was synthesized by Synopsys' FPGA Compiler or Design Compiler, the following error may occur in Translate (NGDBUILD):
ERROR:NgdHelpers:406 - The LUT2_L symbol "U1/add_628/add_628/A_LUT_4" does not have any programming information. The behavior of a LUT2_L symbol must be defined by an INIT property or an EQN property.
This will repeat for many instances of LUT components that do not have the proper attributes. The "LUT2_L" mentioned in this instance can also refer to other LUT components, like LUT3 or LUT4 and may not necessarily include the "_L".
This issue is similar to the one described in (Xilinx Solution 5048), but in this case the commands mentioned (uniquify and replace_fpga) are not used when synthesizing.
This error may occur if identical Designware components are inferred in different levels of hierarchy in the design.
To work around this issue, compile the levels of hierarchy that contain the duplicate Designware components individually and place a "dont_touch" attribute on that level. To find the levels that contain these instances, look at the error messages. For example, if the errors included these instances:
then you know that components instantiated as U1 and U2 both have adders that have been inferred using identical Designware components. The name "add_628" in this case is an inferred adder; you may see other names referring to arithmetic components like subtractors, comparators, etc.
In this case, U1 and U2 instantiate modules lower_a and lower_b. Compile one of these levels on its own and place a dont_touch before moving on to the rest of the design. One could also do the same for lower_b as well. This must be done if the same module is instantiated more than once, regardless of what components are inferred within it.