AR# 59624

MIG 7 Series - Can the input system clock (sys_clk) be driven by the IBUFDS_GTE2?

描述

In order to reduce the number of oscillators required is it possible to drive the MIG sys_clk from an IBUFDS_GTE2?

解决方案

This is not possible as the sys_clk must be routed on the CLOCK_DEDICATED_ROUTE BACKBONE and the IBUFDS_GTE2 does not have access to this. 

The tools will not generate a DRC error, however it is not a supported clocking topology.

Revision History

08/14/14 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40603 MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines N/A N/A
AR# 59624
日期 08/15/2014
状态 Active
Type 综合文章
器件
IP