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  3. AR 5986X
  4. AR# 59861: XAUI and RXAUI - Vivado 2013.4 and earlier - GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover

AR# 59861

XAUI and RXAUI - Vivado 2013.4 and earlier - GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover

描述

When using XAUI v12.1 or RXAUI v4.1 and earlier, production reset GTP and GTH DRP sequence can end up in a hung state that requires reconfiguration to recover (Xilinx Answer 60033). 

The failure is only seen when a second reset is issued to the core while a previous reset sequence is underway. 

The reset sequence is started automatically after configuration, so this could happen if the main core reset is toggled shortly after the device is configured. 

Affected core configurations that use the DRP reset logic are:

XAUI 7-Series GTP and GTH
DXAUI 7-Series GTP
RXAUI 7-Series GTP

The failure happens due to a DRP register setting getting stuck with a 16-bit Rx data width instead of the required 20-bit data width. 

XAUI, DXAUI and RXAUI use a 20-bit data width during normal operation, but DRP logic sets data width to16-bit during a reset sequence to avoid production reset issues (see GT Transceiver UG for more information on required reset logic).  

The failure is only seen when a second reset is issued to the core while a previous reset sequence is underway.

解决方案

To work around this, the second DRP write can be changed to ensure that the data width is set back to 20 instead of relying on the initially read value which can get stuck at 16, if a reset is issued during the DRP sequence.  

The DRP update should be made to <core_name>_*_gtrxreset_seq.v/vhd (if used also change <core_name>_*_gtrxrate_seq.v/vhd and <core_name> ).

For VHDL change the following:

 

To:

      --write to 20-bit mode

      WHEN wr_20 =>

        ...

         drpdi_o <= rd_data(15 downto 12) & '1' & rd_data(10 downto 0); --restore 20-bit mode



For Verilog change the following:

//write to 20-bit mode

                wr_20 : begin

                        ....

                        drpdi_o = rd_data[15:0]; //restore user setting per prev read

                end

       To:

//write to 20-bit mode

                wr_20 : begin

                         ....

                        drpdi_o = {rd_data[15:12], 1'b1, rd_data[10:0]}; //restore 20-bit

                end

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54249 IP Release Notes and Known Issues for LogiCORE RXAUI for Vivado 2013.1 and newer tool versions N/A N/A
54666 LogiCORE IP XAUI - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 59861
日期 04/17/2014
状态 Active
Type 综合文章
IP