To work around this, the second DRP write can be changed to ensure that the data width is set back to 20 instead of relying on the initially read value which can get stuck at 16, if a reset is issued during the DRP sequence.
The DRP update should be made to <core_name>_*_gtrxreset_seq.v/vhd (if used also change <core_name>_*_gtrxrate_seq.v/vhd and <core_name> ).
For VHDL change the following:
To:
--write to 20-bit mode
WHEN wr_20 =>
...
drpdi_o <= rd_data(15 downto 12) & '1' & rd_data(10 downto 0); --restore 20-bit mode
//write to 20-bit mode
wr_20 : begin
....
drpdi_o = rd_data[15:0]; //restore user setting per prev read
end
To:
//write to 20-bit mode
wr_20 : begin
....
drpdi_o = {rd_data[15:12], 1'b1, rd_data[10:0]}; //restore 20-bit
end
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
54249 | IP Release Notes and Known Issues for LogiCORE RXAUI for Vivado 2013.1 and newer tool versions | N/A | N/A |
54666 | LogiCORE IP XAUI - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions | N/A | N/A |
AR# 59861 | |
---|---|
日期 | 04/17/2014 |
状态 | Active |
Type | 综合文章 |
IP |