AR# 60050


MIG 7 Series DDR3/DDR2 - cmp_data_r and dbg_rddata_r are not aligned


Version Found: MIG 7 Series v2.0
Version Resolved: See (Xilinx Answer 54025)

The MIG 7 Series generated example design contains a traffic generator which can detect data errors.

When looking at the compared data "cmp_data_r" vs. the actual read data "dbg_rddata_r" they appear misaligned but no compare errors are detected.


This is safe to ignore as the internal compare logic is correctly aligned and comparing the correct data.

This can be difficult to characterize if actual data errors occur.

The misalignment between cmp_data_r and dbg_rddata_r should not be more than 5 cycles off so careful attention is required to determine which cycle cmp_data_r should actually be used to compare against dbg_rddata_r.

Revision History
04/16/2014 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60050
日期 04/16/2014
状态 Active
Type 已知问题
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