AR# 60055


IP Soft Error Mitigation - Timing warning for the VIO core


If a DRC check or timing analysis is performed on the synthesized design, Timing warnings can be reported.


This timing warning is not significant, and can be safely ignored. 

Instead, timing analysis should be performed post implementation to verify the design meets timing.

An example warning message is below:

TIMING-17#1 Warning

Non-clocked sequential cell 

The clock pin example_hid/example_vio/inst/DECODER_INST/Bus_data_out_reg[*]/C is not reached by a timing clock

Related violations: <none>

This is a tool issue relating to the VIO core, currently no fix is planned.


If timing is all met post implementation, the design will have no timing related issues.



Answer Number 问答标题 问题版本 已解决问题的版本
54642 Soft Error Mitigation IP Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 60055
日期 04/17/2014
状态 Active
Type 综合文章
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