AR# 60198


LogiCORE Tri-Mode Ethernet MAC v9.0 and earlier - UltraScale Devices - GMII/RGMII - Timing not met on I/O interface


When using the Tri-mode Ethernet MAC core to target an UltraScale device with a GMII/RGMII interface, timing violations can be seen on the I/O to flop paths.


The fix to meet timing for both of these interfaces is to lock the below resources.
Receive path -  Lock I/Os and Clock Buffers to the same clock region.

The Receive clock should go to two clock Buffers.
One dedicated clock buffer will provide clock to Flops inside the I/Os and the other clock buffer to the rest of the receive logic.
Note: In v8.3 TEMAC in Vivado 2014.4, the relative file needs to be modified to add an extra buffer.
However, this is no longer required with v9.0 TEMAC in Vivado 2015.1.

Transmit path -  Lock I/Os, Clock Buffers and MMCM in the same clock region.
If the tool does the correct placement without locking the resources as outlined above then the design meets timing.



Answer Number 问答标题 问题版本 已解决问题的版本
54251 LogiCORE Tri-Mode Ethernet MAC - Release Notes and Known Issues for Vivado 2012.1 and newer tool versions N/A N/A
AR# 60198
日期 03/11/2015
状态 Active
Type 综合文章
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