This Release Note is for the System Management Wizard v1.0 Rev1 released in Vivado 2014.1 and contains the following information:
The System Management Wizard v1.0 Rev1 supports the Xilinx UltraScale FPGAs.
The System Management Wizard generates a HDL wrapper to configure a single UltraScale FPGA SYSMONE1 primitive for user-specified channels and alarms.
New Features in v1.0 Rev1
Bug Fixes in v1.0 Rev1
Known Issues in v1.0 Rev1
System Management wiz example design in 2014.1 will fail to meet timing requirement when AXI4_Lite Interface is selected.
Workaround: Add BUFG on clock path in example design.
System Management wiz example simulation in 2014.1 will fail with the error below:
This error message is also applicable to VUSER2. This is a simulation model issue.
Workaround: There is currently no workaround for this issue. The Design works with no issues in Hardware.
15/04/14 - Initial Release