Version Found: 2.0 Rev 2
Version Resolved: See (Xilinx Answer 54025)
For MIG 7 Series QDRII+ designs, the read data clocks (CQ/CQ#) must be placed on the two MRCC_P or MRCC_N pins available in the same bank as the read data or in an adjacent bank to it.
This is because the MRCC pins have access to drive BUFMR's which have access to the PHASER_IN's.
MIG allows 2 CQ/CQ# pairs to be placed in the same bank when using the Fixed Pin Out mode in the MIG GUI.
If 2 CQ/CQ# pairs are placed in the same bank then the following critical warning and errors may be seen:
[Synth 8-3352] multi-driven net qdriip_cq_p with 1st driver pin 'qdriip_cq_p' ["/group/bcapps/criley/escalations/1002295/project_1_ex/mig_7series_0_example/mig_7series_0_example.srcs/sources_1/imports/rtl/example_top.v":74]
[Place 30-475] IO terminal qdriip_cq_n with IOStandard HSTL_I_DCI is not placeable anywhere in the device.
Please check whether the IOSTANDARD is compatible with the target device.
There are only 2 BUFMR's available in each bank so placing more than 1 CQ/CQ# pair is not physically possible.
The 2nd CQ/CQ# pair must be moved to MRCC_P or MRCC_N pins in an adjacent bank.
04/16/2014 - Initial Release