AR# 60687

MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1 released with Vivado 2014.2 that provide additional read margin for data rates above 1333Mbps


The MIG 7 Series v2.1 DDR3 calibration algorithm released in Vivado 2014.2 includes changes that positively impact the available read margin. 

The updates are only enabled within generated designs operating above 1333Mbps. 

This answer record includes information regarding the updates and whether the updates are recommended within existing DDR3 systems.


Recommendations for updating MIG Versions:

No RTL changes are included for interfaces operating below 1333Mbps.

For interfaces operating above 1333Mbps, the updated v2.1 DDR3 design available in 2014.2 is recommended but not required.

Systems already in production that have completed system testing with no read margin failures do not need to update.

For new designs, updating to v2.1 to make use of the latest calibration algorithm is recommended.

Determining if Read Margin is Causing Data Errors:

If data errors are seen in pre-MIG v2.1 designs operating above 1333Mbps, care should be taken to ensure the errors are due to small read margin.

Strict adherence to all MIG PCB guidelines and careful attention to IBIS simulation must be completed first.

Additionally, the data errors should be analyzed to determine if a small read window is the root cause.

Review the DDR3 Debugging Data Errors section of UG586 for assistance in isolating the data error.

IDELAY Reference Clock Changes above 1333Mbps:

A part of the read margin improvements available in v2.1 comes from an increase in the IDELAY reference clock frequency (ref_clk) which provides finer tap resolution. 

Previously, MIG always used a 200MHz IDELAYCTRL reference clock.

With the new algorithm, designs above 1333Mbps use the following IDELAYCTRL reference clock frequency:

  • 400 MHz for -2 and -3 speed grades
  • 300 MHz for -1 speed grade
MIG 7 Series v2.1 was designed to remain compatible with prior versions in which case a 200MHz input "ref_clk" is still required.

MIG 7 Series v2.1 will use that 200MHz "ref_clk" to clock the XADC and then an extra MMCM is added to generate the 300MHz or 400MHz IDELAYCTRL reference clock required for the v2.1 calibration updates.

If a 200MHz input system clock "sys_clk" is used, users have the option to select "Use System Clock" for the reference clock in the MIG GUI in which case MIG will automatically connect up and drive the XADC and the extra MMCM to generate the 300MHz or 400MHz clock.

If the option "No Buffer" is selected in the MIG GUI for the reference clock the XADC and extra MMCM are still automatically connected up but the user can supply the 200MHz input "ref_clk" from elsewhere in their design internally.

See UG586 for information on the Reference Clock options. 

Additional Information:

See (Xilinx Answer 59167) for information on the Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces.

Revision History:
06/16/2014 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60687
日期 07/01/2014
状态 Active
Type 综合文章