AR# 60706

UltraScale FPGA Transceiver Wizard v1.3 - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the UltraScale FPGA Transceiver Wizard v1.3, released with Vivado Design Suite 2014.2.


Title: Unsupported programmable divider causes core generation error.

Description: Some low line rate, wide data width Wizard configurations result in the inferred use of a currently-unsupported programmable divider setting, producing the following core generation error message:

ERROR: [] <component_name>: The requested configuration requires a Programmable divider value that is not supported at this time.

For your low line rate configuration, please choose narrower internal and external data widths.

This same error may also occur as a result of enabling the selectable TXOUTCLK frequency feature and choosing a low-frequency TXOUTCLK value.

Work-around: Choose narrower user and internal data width options.

If using the selectable TXOUTCLK frequency option, choose a higher-frequency value.

To Be Fixed: 2014.4

CR: 776705

Status: Resolved in 2014.4 core v1.4 Rev1

Title: Line rate and clock frequency configuration options are not currently limited by package type or the -1L VCCINT=0.90V option.


The Kintex UltraScale Architecture Data Sheet (DS892) specifies that FBV package types have a lower GTH maximum line rate than other package types, for some device speed grades.

Additionally, DS892 specifies that various GTH clock frequency ranges differ between VCCINT=0.90V and VCCINT=0.95V operation for -1L speed grade devices.

Neither of these two types of restrictions are enforced by the Wizard.

Work-around: When configuring the Wizard for a device with either an FBV package, or a -1L speed grade that you intend to operate at VCCINT=0.90V, consult the relevant Data Sheet for transceiver operational limits.

To Be Fixed: 2015.1

CR: 793735, 798382

Status: Resolved in 2015.1 core v1.5 Rev1

Title: RXSLIDE in PMA or AUTO mode has no effect in raw mode configurations.

Description: For Wizard configurations where the receiver uses raw mode (no data decoding), which use the receiver elastic buffer, and which use RXSLIDE in PMA or AUTO mode, assertions of RXSLIDE are ignored and do not cause bit slips as desired.

Work-around: In the optional ports enablement interface section of the Wizard GUI Structural Options tab, mark the checkbox to enable the rxphdlypd_in port In your design, drive each bit of this port to 0.

To Be Fixed: 2014.3

CR: 801413

Status: Resolved in 2014.3 core v1.4

Title: Reset controller helper block input gtwiz_reset_all_in may reset TX and RX resources in parallel.


The Wizard reset controller helper block input gtwiz_reset_all_in is designed to reset TX resources, followed by RX resources, in sequence.

An issue with bit synchronization delay variability can result in TX resources instead being reset in parallel with RX resources.

For configurations where TX must be reset before RX for stability reasons (for example, when operating in loopback), use of the following work-around is recommended.

Work-around: Tie or drive the gtwiz_reset_all_in input low, and use other reset controller helper block inputs to perform the equivalent sequential reset procedure.

For example, in sequence:

  1. Pulse gtwiz_reset_tx_pll_and_datapath_in
  2. Wait for the rising edge of gtwiz_reset_tx_done_out
  3. Pulse either:

    a. gtwiz_reset_rx_datapath_in (if TX and RX data paths use the same PLL), or

    b. gtwiz_reset_rx_pll_and_datapath_in (if TX and RX data paths use different PLLs)

  4. Wait for the rising edge of gtwiz_reset_rx_done_out

To Be Fixed: 2014.3

CR: 805664

Status: Resolved in 2014.3 core v1.4

Title: Receiver termination voltage limited to FLOAT for DC coupled links.

Description: Wizard configurations which use DC link coupling must choose FLOAT for receiver termination.

This selection is available but is not currently enforced by the Wizard.

Work-around: When customizing the Wizard core instance in the GUI, select FLOAT for the Termination field in the Receiver: Advanced section of the first tab.

To Be Fixed: 2015.3


Status: Resolved in 2015.3 core v1.6

Title: GTH CPLL reset disrupts TXOUTCLK in some UltraScale engineering sample devices.

Description: In GTH configurations targeting Kintex UltraScale ES1/ES2 and Virtex UltraScale ES1 engineering sample devices, resetting the CPLL will disrupt the TXOUTCLK signal, even when the CPLL is used for the RX data path and a QPLL is used for the TX data path.

This is due to the presence and operation of the CPLL calibration procedure which briefly takes control of the TXOUTCLK source during CPLL reset, irrespective of which resources the CPLL clocks.

Work-around: This behavior cannot be avoided in GTH configurations targeting the affected engineering sample devices.

If runtime disruption to TXOUTCLK in response to resetting the CPLL is not tolerable in configurations where the CPLL drives only RX resources, take care to reset and achieve lock on the CPLL prior to, or separate from bringing up TX resources.

Note: This limitation has been added to the UltraScale FPGAs Transceivers Wizard Product Guide (PG182) v1.6.

AR# 60706
日期 10/16/2015
状态 Active
Type 版本说明