AR# 60712

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LogiCORE IP G.709 FEC Encoder/Decoder - Why do the post implementation/post synthesis simulation results vary from the behavioral simulation results in 2014.2 when VHDL is used

描述

Why do the post implementation/post synthesis simulation results of the G.709 FEC Decoder vary from the behavioral simulation results in 2014.2 when the simulation language is VHDL?

解决方案

The Behavior simulation is correct. This is a known issue affecting VHDL only.
 
It is restricted to cases using the Decoder and affects only UltraScale devices.
 
The workaround is to use Verilog as the simulation language.
 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54477 LogiCORE IP G.709 FEC Encoder/Decoder - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 60712
日期 07/28/2014
状态 Active
Type 综合文章
IP
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