AR# 60725


LogiCORE Video to SDI TX Bridge v1.0 - How should I connect the core's clock enables?


I am trying to determine the proper connections between the Video to SDI TX Bridge, AXI4-Stream to Video Out, Video Timing Controller, and SMPTE SDI cores.

How should the core's clock enables be connected?


There are two output signals from the Video to SDI TX Bridge core that need to be connected to the AXI4-Stream to Video Out  core.

There is also one clock enable from the AXI4-Stream to Video Out core that needs to be connected to the VTC.

  • Signals driven by the Video to SDI TX Bridge:
    • tx_ce_sd - 1-bit - Three copies of this signal should be connected to the SDI core's tx_ce port (see (Xilinx Answer 60724) for more information).
    • vid_ce - 3-bits - Any one bit from this signal should be used to drive the AXI4-Stream to Video Out core's vid_io_out_ce port.
  • Signals driven by the AXI4-Stream to Video Out:
    • vtg_ce - 1-bit - This signal should drive the gen_clken port on the Video Timing Controller.



Answer Number 问答标题 问题版本 已解决问题的版本
54544 LogiCORE Video to SDI TX Bridge Core - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
AR# 60725
日期 08/20/2014
状态 Archive
Type 综合文章
People Also Viewed