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AR# 60845

Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation

描述

Version Found: MIG 7 Series v2.0 Rev2
Version Resolved: See (Xilinx Answer 54025)

For MIG 7 Series v2.0 Rev2 RLDRAM3 designs the SIM_BYPASS_INIT_CAL parameter is always set to "FAST" in both <core_name>_mig.v and <core_name>_mig_sim.v by default.

"FAST" should only be used for behavioral simulations and will cause calibration and data failures in hardware.

For synthesis, implementation, and hardware testing SIM_BYPASS_INIT_CAL should be set to "NONE".

This issue affects RLDRAM3 designs only.

解决方案

To work around this issue you must modify the top-level parameter SIM_BYPASS_INIT_CAL inside "<core_name>_mig.v" to the following:

SIM_BYPASS_INIT_CAL="NONE",

Revision History

06/09/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60845
日期 06/11/2014
状态 Active
Type 设计咨询
器件
Tools
IP
的页面